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RTI-MP

For graphical setup of multiprocessor and multicore structures

The multiprocessor option for Real-Time Interface (RTI-MP) supports multiprocessor and multicore systems based on dSPACE‘s PHS hardware and helps to increase the performance of real-time simulations.

Application Areas

The multiprocessor option for Real-Time Interface (RTI-MP) supports multiprocessor and multicore systems based on dSPACE‘s PHS hardware and helps to increase the performance of real-time simulations. It assists in setting up multiprocessor networks, including the communication channels. Multicore applications are configured in the same way as multiprocessor applications.

Working with RTI-MP

RTI-MP lets you partition your system model and allocate the parts to the processors or cores by using simple drag & drop operations. Each processor submodel can be adjusted individually for optimum performance, including step sizes, integration algorithms and trigger conditions. After specification, you can implement your model on the processor boards with a single mouse click. Build procedures can also be automated with the help of scripts.

RTI-MP for dSPACE Simulator

In practical development work, several processor boards are often connected to one networked dSPACE Simulator, and highly dynamic simulation models exchange simulation data via Gigalink modules. An easy way of specifying the topology of a whole network is therefore essential. RTI-MP offers special blocks to configure Gigalink communication within Simulink. The real-time application, including realtime synchronization between the simulators, can then be generated with a single click.

Key Benefits

RTI-MP offers a maximum of convenience to accomplish tasks such as:

  • Partitioning the system for optimum processor load
  • Defining interprocessor communication channels
  • Producing the communication code for a network of several processors or cores

System dynamics can be designed in Simulink. 

Functionality Description
Partitioning the Simulink® model
  • Adding Simulink blocks for model partitioning via drag & drop
  • Generating highly optimized real-time simulation engine and communication code
  • Support of triggered subsystems distributed over multiple processors or cores
  • Full support of interprocessor interrupts
Optimizing speed and accuracy
  • Integration algorithm and step size specific to each processor and core
  • Single/multitasking mode
  • Swinging buffer or shared memory communication mechanism for each individual connection
  • Interprocessor communication at different sampling rates
Testing and documenting
  • Documentation of entire multiprocessor setup
Implementing the model on multiprocessor or multicore hardware
  • Automatic code generation for one processor or complete system
  • Download and start with a single click
  • Data acquisition with time stamps
  • Profile information for communication channels for optimizing the partitioning
Communication mechanisms
  • Communication via high-speed optical connection (Gigalink) enabled
  • Asynchronous data transfer in shared memory mode
  • Synchronized and unsynchronized block data transfer in swinging buffer mode
  • Buffering and unbuffering of data via communication connection

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