The FPGA Programming Blockset now supports MathWorks© HDL CoderTM for modeling parts of the FPGA model with Simulink® blocks. This feature lets you use existing Simulink models directly as part of your FPGA application. For example: You can use a Simulink model of a controller for first functionality tests before you optimize the FPGA utilization of the controller.
However, Xilinx® Vivado® Design Suite and Xilinx® VitisTM Model Composer are still required to build the entire FPGA application.
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