RTI FPGA Programming Blockset

dSPACE 系统中集成 FPGA 模型

RTI FPGA Programming Blockset是一种 Simulink 模块组,它能通过 Xilinx ® System Generator Blockset将dSPACE 系统创建的 FPGA 模型加以利用

The end of life of the dSPACE PHS (peripheral high-speed) hardware for modular systems is planned for December 31, 2024. You can still buy the related products up to and including December 31, 2021. New Releases of dSPACE software will still support the dSPACE PHS hardware for modular systems until at least the end of 2023. Although the RTI FPGA Programming Blockset still supports PHS hardware, we advise against using the PHS hardware products in new projects. For new projects we recommend that you use SCALEXIO, the latest dSPACE technology for modular real-time systems.

应用领域

RTI FPGA Programming Blockset是一种 Simulink 模块组,它能通过 Xilinx ® System Generator Blockset将dSPACE 系统创建的 FPGA 模型加以利用该模块组配有多个 RTI 接口模块,以便实现安装的 FPGA 芯片与板卡 I/O 之间的调用以及 FPGA 芯片主处理器之间的通讯。

该模块组可用于下列 dSPACE 可编程的 FPGA 平台:

  • DS2655 FPGA 基板及其 I/O 模块。
  • DS6601/DS6602 FPGA Base Board及其 I/O 模块。
  • MicroAutoBox II 1401/1511/1514 和 1401/1513/1514(带有 I/O 扩展模块)。
  • MicroAutoBox III 1403/1511/1514 和 1403/1513/1514(带有 I/O 扩展模块)。
  • MicroLabBox。

快速控制原型 (RCP) 和硬件在环 (HIL) 仿真的典型应用领域是:

  • 汽车、工业自动化、医学工程及航空航天行业的项目
  • 电力传动系统中的信号预处理、新接口适配、超快控制环及新概念的设计和测试

主要优点

dSPACE FPGA 平台提供Xilinx ® FPGA ,您可以利用 Simulink 中的 Xilinx ® System Generator ,以图形方式为其实现一个应用。RTI FPGA Programming Blockset 能将 FPGA 模型集成在 dSP Simulink 模型中,并最终运行在 dSPACE硬件上。RTI FPGA Programming Blockset 提供一种便捷的方式连接I/O 板卡的I/O驱动组件,对基于处理器计算节点的连接进行建模(SCALEXIO 处理器硬件, MicroLabBox 或者MicroAutoBox ))。数据交换功能支持定点数据类型和浮点数据类型。因此,FPGA 编程模块组将会无缝集成在 Simulink 环境中。借助 FPGA 模块组,您可以直接从 Simulink 对 FPGA 或处理器进行合成、构建和编程,极其便利。在运行时,您可以访问变量,并对其进行跟踪或修改,而无需修改模型。

另外,手写代码接口还能让您通过 VHDL(VHSIC 硬件描述语言)或 Verilog,对 FPGA 板卡进行编程。

Functionality Description
General
  • Integrating an FPGA model on a dSPACE FPGA platform
  • I/O configuration
  • Automatic generation of a processor model template on the basis of an FPGA application
FPGA interface
  • Programming the FPGA with the Xilinx ® System Generator
  • Integrating an FPGA model created with the Xilinx ® System Generator
  • Offline simulation in Simulink
Handcode interface
  • Programming the FPGA in VHDL or Verilog
I/O access
  • Connecting the FPGA model with analog and digital input and output signals with the RTI FPGA Blockset
Processor-FPGA communication
  • Connecting the FPGA model with the processor model running on the computation node (SCALEXIO processing hardware, MicroLabBox or MicroAutoBox)
  • Access types for system bus communication with the dSPACE FPGA platforms: register, register groups, buffer
Inter-FPGA communication between SCALEXIO FPGA base boards
  • Via I/O Module Slots offers lowest latencies

  • Via MGT Module provide highest bandwidth

  • Via IOCNET offers highest flexibility

Asynchronous tasks
  • Implementing interrupt-driven tasks in the processor model triggered from the FPGA model
Variable access 1)
  • Tracing of register values, e.g., dSPACE in ControlDesk directly without model changes
  • Changing constant values during run time of the FPGA application without modeling
Remote FPGA build
  • Support of separate PCs for performing the FPGA build so that the PC used for modeling is not blocked
  • The build process can be observed using an extra tool
1) 可用于SCALEXIO系统、MicroAutoBox和带有RTI FPGA Programming Blockset FPGA Interface 子库的MicroLabBox。

  • RTI FPGA Progammable Blockset 产品信息, PDF, 英語, 792 KB
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