SCALEXIO EMH Solution为基于处理器的电驱动 HIL 仿真提供了一个全面的 ConfigurationDesk I/O 库。
SCALEXIO EMH Solution最多可以针对两个电驱动装置的系统来定义 I/O 功能。所需的FPGA基板(DS6601、DS6602或DS2655)是在ConfigurationDesk中配置的。凭借预定义的功能块,用户无需编程,也无需生成 FPGA 代码。DS2655M1和DS6651 Multi-I/O Modules和集成式角度处理单元 (APU) 使用高分辨率I/O,支持位置传感器仿真 (PSS) 和脉宽调制 (PWM) 领域的应用。通过可变 I/O 通道映射和对多达五个DS2655M1或五个DS6651 Multi-I/O Modules的灵活支持,完全发挥硬件的潜力。如果驱动控制器需要更高的仿真分辨率,无需更改硬件,即可无缝切换到基于 FPGA 的仿真。EMH Solution FPGA配备有四个内部 APU,这些单元在FPGA基板上运行,用于执行本地位置计算。此外,通过 IOCNET 最多可将六个主 APU 作为全局参照位置源。每个位置传感器均可进行配置,以便将十个 APU 中的任意一个作为位置源。
根据 DS2655M1 模块数量的不同,可用 I/O 通道数量也有所不同。
位置传感器仿真 (PSS) 的主要功能
Function | Description | I/O Requirements per Function | |
---|---|---|---|
Resolver Out | Simulation with configurable pole pair number, offset angle, transformer ratio. Excitation input signal delay. Output amplitude and phase error manipulation. | 2 |
Excitation: 1x Analog In Sin/Cos: 2x Analog Out |
Sine Encoder Out | Simulation with configurable number of lines, output amplitude and DC offset | 2 | A,B, Index: 3x Analog Out Or 1 6x Analog Out |
Incremental Encoder Out | Simulation with configurable number of lines and offset angle | 2 | A,B, Index: 3x Digital (Out) Or 1 6x Digital (Out) |
Hall Encoder Out | Simulation with configurable pole pair number, offset angle, angle-dependent pulse activation/deactivation | 2 | A,B,C: 3x Digital (Out) Or 1 6x Digital (Out) |
Analog Wavetable Encoder Out | Output with freely designable analog shape format for 360 degrees with up to 16383 values and optional linear interpolation for intermediate values. Configurable number of waveforms per revolution. | 3 | 1x Analog Out |
Digital Wavetable Encoder Out |
Output with freely designable digital shape format for 360 degrees with up to 16383 values. Configurable number of waveforms per revolution. | 3 | 1x Digital (Out) |
脉宽调制 (PWM) 的主要功能
Function | Description | I/O Requirements per Function | |
---|---|---|---|
Six-Channel PWM In | Supporting duty cycle, period time, latch time and dead time2 measurement and configurable interrupt generation (latch-based measurement), oversampling, downsampling Optional external triggering Optional2 dead time violation interrupt generation | 2 |
Gates: 3x Digital (In) Or 2 Optional ext. trigger: Optional latch pulse: 1x Digital (Out) |
Single-Channel PWM In | Combined edge-based and latch-based measurement of duty cycle and frequency | 4 | 1x Digital (In) |
Single-Channel PWM Out | PWM generation with variable frequency and duty cycle | 4 | 1x Digital (Out) |
基本 I/O 功能
Function | Description | Number of Functions per FPGA Base Board | I/O Requirements per Function |
---|---|---|---|
Multi-Bit In | Standard digital input functionality for variable number of channels | 4 | 1-50 Digital (In) |
Multi-Bit Out | Standard digital output functionality for variable number of channels | 4 | 1-50 Digital (Out) |
Multi-Voltage In | Standard analog input functionality for variable number of channels | 4 | 1-25 Analog In |
Multi-Voltage Out | Standard analog output functionality for variable number of channels | 4 | 1-25 Analog Out |
推动创新进程。我们始终在技术开发的最前沿。
欢迎订阅我们简讯,了解我们的专业技术以及产品。希望我们的成功案例能够对您有所帮助。快速了解仿真和验证的最新信息。欢迎订阅/管理dSPACE简讯和dSPACE航空速报。