The RTI FPGA Programming Blockset is a Simulink blockset for using an FPGA model created with a dSPACE system using the Xilinx® System Generator Blockset.
The RTI FPGA Programming Blockset is a Simulink blockset for using an FPGA model created with a dSPACE system using the Xilinx® System Generator Blockset. It provides RTI blocks for implementing the interface between the FPGA mounted on a dSPACE board and its I/O, and the interface between the dSPACE FPGA board and its computation node.
The blockset can be used with the following dSPACE FPGA platforms, which provide user-programmable FPGAs:
Typical application scenarios for rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulation are:
The dSPACE FPGA platforms provide a Xilinx® FPGA for which you can implement an application graphically by using Xilinx® System Generator in Simulink. The RTI FPGA Programming Blockset lets you integrate the resulting FPGA model in a Simulink model that runs on dSPACE hardware. The RTI FPGA Programming Blockset gives you a convenient way to connect the I/O board’s I/O driver components and to model the connection to a processor-based computation node (DS1006 or DS1007, SCALEXIO processing hardware, MicroLabBox or MicroAutoBox). The data exchange supports fixed-point data types as well as floating-point data types. Thus, FPGA programming is seamlessly integrated into the Simulink environment. With the FPGA blockset, you can synthesize, build and program the FPGA or processor directly from Simulink for optimal convenience. During run time, you can access variables to trace or modify them, without having to modify the model.
Alternatively, the handcode interface lets you program the FPGA boards in VHSIC Hardware Description Language (VHDL) or Verilog.
|Inter-FPGA communication between SCALEXIO FPGA base boards||
|Remote FPGA build||
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