FPGA Programming Blockset

The FPGA Programming Blockset is a Simulink® blockset based on the AMD® Vitis™ Model Composer HDL Library for allowing the integration of FPGA models into a dSPACE system.

Scalable

Modular and scalable architecture for tailored test solutions

Best-in-Class for Closed Loop

Fastest real-time calculation of large and complex simulation models

Convenient Model-Based Approach

Comfortable design of FPGA applications within a Simulink environment

Application Areas

The FPGA Programming Blockset is a Simulink blockset based on the AMD® Vitis™ Model Composer HDL Library. It provides blocks for implementing the interface between the FPGA mounted on a dSPACE board and its I/O, and the interface between the dSPACE FPGA board and the processor.

Despite the model-based approach, the FPGA Programming Blockset allows a very high degree of freedom during implementation. For example, it is possible to implement subsystems with the HDL Coder^TM or to use multiple clock domains. It also allows the coupling of multiple dSPACE FPGAs.

Typical application scenarios for rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulation are:

Projects in the automotives, industrial automation, medical engineering, and aerospace industries
Signal preprocessing, adapting new interfaces, very fast control loops, designing and testing new concepts for electrified powertrains

Key Benefits

Graphically programmable with AMD® Vitis™ Model Composer HDL Library or HDL Coder in Simulink®
FPGA build sever for Linux for an accelerated build process
Integrate the resulting FPGA design into a real-time application
Synthesize, build, and program an FPGA or processor directly from Simulink for optimal convenience

Benefits in Detail

The dSPACE FPGA platforms provide various cutting-edge AMD® Vitis™ FPGAs that can be programmed graphically with AMD® Vitis™ Model Composer HDL Library in Simulink®. The platforms let you integrate the resulting FPGA design into a real-time application that runs on dSPACE hardware.

The blockset also provides a convenient way to connect the I/O board’s I/O driver components and to model the connection to a processor-based computation node (SCALEXIO processing hardware, MicroLabBox, or MicroAutoBox). The data exchange supports fixed-point data types as well as floating-point data types.

To provide maximum flexibility in developing FPGA applications, you can integrate custom IP cores into your Simulink FPGA model or use HDL CoderTM to model parts of the FPGA design. With the FPGA blockset, you can synthesize, build, and program an FPGA or processor directly from Simulink for optimal convenience.

By using a dSPACE FPGA Build Server under Windows or Linux, build processes can be outsourced to the server and monitored with a monitoring tool. The separation of modeling and build processes enables optimized and independent workflows.

During run time, you can access variables to trace or modify them without having to modify the model. An FPGA scope even allows for in-depth analysis of your design.

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Functionality	Description
General	Integrating an FPGA model on a dSPACE FPGA platform I/O configuration Automatic generation of a processor model template on the basis of an FPGA application
FPGA interface	Programming the FPGA with the AMD® Vitis™ Model Composer HDL Library. Integrating an FPGA model created with the AMD® Vitis™ Model Composer HDL Library. Offline simulation in Simulink^®
I/O access	Connecting the FPGA model with analog and digital input and output signals with the FPGA Blockset
Processor-FPGA communication	Connecting the FPGA model with the processor model running on the computation node (SCALEXIO processing hardware, MicroLabBox or MicroAutoBox) Access types for system bus communication with the dSPACE FPGA platforms: register, register groups, buffer, and Simulink buses
Inter-FPGA communication between SCALEXIO FPGA base boards	Via I/O Module Slots offers lowest latencies Via MGT Module provide highest bandwidth Via IOCNET offers highest flexibility
Asynchronous tasks	Implementing interrupt-driven tasks in the processor model triggered from the FPGA model
Variable access	Tracing of register values, e.g., dSPACE in ControlDesk directly without model changes Changing constant values during run time of the FPGA application without modeling
FPGA build sever	Supports separate PCs to perform FPGA builds, so that the PC used for modeling is not blocked FPGA build sever available for Windows and Linux The build process can be monitored using a separate tool
Support of MathWorks^® HDL Coder^TM	Modeling parts of the FPGA model with Simulink blocks Use existing Simulink models directly as part of your FPGA application Support of offline simulation and FPGA builds

Optional Hardware	Boards and Variants
SCALEXIO	DS2655 FPGA Base Board DS6601 FPGA Base Board DS6602 FPGA Base Board I/O modules: DS2655M1 DS2655M2 DS6651
MicroAutoBox	All variants of the MicroAutoBox II with DS1514 FPGA board All variants of the MicroAutoBox III with DS1514 FPGA board
MicroLabBox / MicroLabBox II	All variants

The FPGA Programming Blockset is a Simulink® blockset based on the AMD® Vitis™ Model Composer HDL Library for allowing the integration of FPGA models into a dSPACE system.

Scalable

Best-in-Class for Closed Loop

Convenient Model-Based Approach

Application Areas

Benefits in Detail

This sounds interesting. Get in touch:

More In-depth Information about FPGA Programming Blockset

Functionality Overview

Supported Hardware

Required Products

ConfigurationDesk

Optional Products

MicroLabBox II

MicroAutoBox III

SCALEXIO Processing Unit

XSG Utils Library

XSG Electric Component Library

XSG Power Electronics Systems

Our Trainings

FPGA Basic

FPGA Electric Drives

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