DS5482 4-Channel Cell Voltage Emulation Board

Compact board for simulating high-voltage batteries at cell level 

With the DS5482, dSPACE offers a versatile 4-channel SCALEXIO board for testing battery management systems (BMS) at voltage level. The product enables compact and cost-effective simulation of high-voltage batteries at cell level with system voltage batteries up to 1,500 V. It can be used for testing BMS in the automotive sector as well as for other applications, for example, in stationary energy storage.

The DS5482 consists of the DS5482 C1 cell emulation board and the DS5482 F1 auxiliary board.

The DS5482 consists of the DS5482 C1 cell emulation board and the DS5482 F1 auxiliary board. To use it, you install it in a 19-inch subrack of a SCALEXIO battery HIL system. The boards are controlled by a dynamic real-time-capable battery power supply model that runs on the HIL system.

The DS5482 is used to map terminal voltages for four battery cells. The board provides balancing currents of up to 5 A.

The DS5482 can also be combined with other boards, e.g., 2-channel boards, in the 19-inch subracks of the HIL system. With four channels per board, the DS5482 is very compact, making optimum use of the installation space and thus reducing the space required for a given number of cells. Thanks to the IOCNET connection, it can also update cell voltages at a rate of up to 10 kHz based on a processor application.

The DS5482 emulates four series connected battery cells. Multiple boards can be connected in series up to a maximum system voltage 1500 V in a HIL system.

Technical Details

Parameters
Specification 1)
Hardware structure
  • 4 cells per board 
  • 64 cells per slot unit 
Voltage range
  • 0... 6 V
Resolution 
  • 0.1 mV
Precision 2) 
  •  ±0.5 mV
Working temperature (environment)
  • 5 ... 40 °C (41 ... 104 °F)
Maximum current (sink/source) 
  • 5 A (peak)
  • 2.5 A (continuous)
Isolation 
  • 1,500 V between the cells and the environment
Connection
  • IOCNET interface to the SCALEXIO real-time system
Maximum update rate for all cells
  • 10 kHz (processor) 
  • 100 kHz (FPGA)
Failure simulation
  • Broken wire between ECU and battery
  • Short circuits of cells
  • High-frequency ripple voltages

1)    Preliminary data. For technical specifications, contact dSPACE.
2)    Laboratory conditions.
 

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