Analysis of large simulation models for ideal distribution onto one or more FPGAs using the dSPACE Electrical Power Systems Simulation Package
When you are creating complex simulation models for power electronic circuits, the models might become too large to be computed on a single FGPA without optimizations. The question then arises as to how you can reduce the computational effort and where, if necessary, the ideal interfaces are to split the model into meaningful subsystems. Here, you have to guarantee that the quality of the results is not worsened by an unfavorable separation.
A concrete example will be used to illustrate a generic approach dSPACE provides for this task.
Model Analysis with Regard to Size and Dependencies
The starting point is the model of an electric vehicle with an onboard charger connected to the power grid by means of a wallbox, created with the MATLAB®/Simulink® Simscape ElectricalTM (Specialized Power Systems) toolbox.
The first step is an analysis of the model, which outputs whether the model can be calculated directly with the available FPGA. The dSPACE Electrical Power Systems Simulation Package (EPSS) offers an analysis function for this purpose. In our case, the result is that the model with its 262,144 matrix sets, each consisting of system, input, output, and pass-through matrices, is too large for the available maximum-speed memory on the FPGA. This large number of matrix sets results from the fact that for the 18 switches included in the model, theoretically all 218 = 262,144 possible configurations could be considered.
If the analysis had shown that the model could be calculated on the FPGA in its entirety, an EPSS file would have been generated for the model, which contains all the data necessary for real-time simulation and can be included in the system's I/O configuration via the dSPACE ConfigurationDesk software. In the case of the onboard charger topology shown above, the overall model is not suitable for simulating the full configurations with all possible switch combinations in real time, so the EPSS file could not be generated.
Modeling Dependencies in the Circuit Diagram
The ANALYZE_SPLITTING block included in EPSS provides a visual representation that shows which model components mathematically belong together and must not be separated. Here, both dependent state variables, specifically dependent capacitor voltages and inductor currents, and the possible effect of switching events on other switching elements are calculated. The elements that belong together are each marked in the same color and thus their dependencies are represented visually.
Checking Possible Splitting Positions
In the schematic diagram, special splitting blocks contained in EPSS (called INTERFACE blocks) can be inserted at various points in the circuit diagram so that the switches are distributed as evenly as possible and no dependency groups are separated. A possible splitting position is shown in the following figure. The INTERFACE block for model splitting was placed so that neither switch groups nor dependent states were separated. A re-execution of the analysis function shows a significant reduction of the matrix sets to be stored on the FPGA from 262,144 to 4,096.
The next step is to check whether the overall system is stable even with the selected splitting point.
Checking the Stability of Possible Splitting Positions
The ANALYZE_SPLITTING block of the EPSS lets you easily evaluate whether the selected position of the INTERFACE block or a set of possible positions of INTERFACE blocks leads to stable system properties per switch configuration. To exclude non-realistic switch combinations and to speed up the computation time, the switching behavior can be configured via the ‘Exclusion of switch combinations’ option. In the present example, the parallel switches of the wallbox and the filter can each be configured as three-phase switches, since they always switch simultaneously.
The results of the analysis are clearly displayed graphically by clicking on the ‘Generate stability results’ button. In addition to the information whether the respective splitting method, which can be selected via the INTERFACE block, leads to a stable, unstable, or marginally stable overall system for the investigated splittingposition, the eigenvalues of the associated (extended) system matrix are also displayed. All results can be conveniently filtered and arranged as desired.
In the present model, it can be concluded from this analysis that the model behaves stably even after inserting the INTERFACE block for Model Splitting, provided that no short circuits occur in the DC/DC converter.
Reducing the Number of Switches by Considering Special Configurations
There are other options to reduce the number of matrix sets in the real-time application besides Model Splitting. First of all, special switch configurations can be modeled more accurately. In the present model, this concerns the switches Sa, Sb, and Sc, which always switch simultaneously. The same applies to the Rprea, Rpreb, and Rprec switches in the filter. These switches can be easily configured as a three-phase switch using the ‘Exclude Switch Combinations’ feature provided in the dSPACE Electrical Power Systems Simulation Package (using the same graphical user interface as for the splitting analysis, configurable in the SETUP block). Alternatively, they can be modeled as resistors and switched during run time using the EPSS ‘Scenarios’ feature. We use a combination of features here, i.e., Sa, Sb, and Sc are modeled as three-phase switches and Sprea, Spreb, and Sprec are configured using scenarios.
Starting Signal for the Real-Time Simulation
After these configurations, the ANALYZE_MODEL analysis function can now be used again to check the real-time capability of the model for the available FPGA. It turns out that an EPSS file can now be generated for the model, allowing it to be run on the real-time system with a preconfigured generic FPGA build included in the dSPACE Electrical Power Systems Simulation Package (without the need for synthesis).
Offline Investigation of the Switching Behavior
The ‘Analyze Switch Combinations’ feature of the dSPACE Electrical Power Systems Simulation Package allows you to analyze the effects on passive elements in the simulation model for a given control of the active switches. Using the OFFLINE_SIMULATION block provided in EPSS, which allows for offline simulation of the circuit by means of special features provided in EPSS, all switch states occurring during the simulation time can be recorded and displayed graphically. In the following illustration, you can see, among other things, that when the gate of devices Q8 and Q9 (IBGT/diode blocks, respectively) is turned on, Diode2 does not turn on until the post-iteration step in response. The gray and white areas always represent a simulation step, the subdivisions within these areas symbolize a set of possible post-iteration steps. In the right-hand part of the picture, you can also get an overview of how often which switching state is used for the considered control of the model.
- A. Kiffe, K. Witting, and F. Puschmann, "Systematic separation of electrical power systems for hardware-in-the-loop simulation," 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), 2017, pp. P.1-P.10, doi: 10.23919/EPE17ECCEEurope.2017.8098995.
- A. Kiffe, K. Witting, and F. Puschmann, "Separation of Power Electrical Circuits for Different Computation Platforms," 2018 20th European Conference on Power Electronics and Applications (EPE'18 ECCE Europe), 2018, pp. P.1-P.10.