Built-In Verification and Validation Support

Three Simulation Modes for Testing

TargetLink performs the three different simulation modes without any changes to the model or the generated code. TargetLink does this automatically in the background.

Although code generators produce virtually flawless results, when compared to manual programming, the generated code still needs to be tested as well as the underlying specification. TargetLink provides powerful and easy-to-use means to verify the generated code. The code tests are performed in the same simulation environment that was used to specify the underlying simulation model. Functional identity has been achieved when the simulation results match. TargetLink provides a three-step verification process which shows at the click of a button whether the specification (the model) and implementation (the generated code) are functionally identical.   

Model-in-the-Loop Simulation

  • Data is recorded for reference plots from the simulation model. Signals from selected blocks and state variables are automatically logged by TargetLink.
  • The model-in-the-loop simulation captures the specified behavior of the model that is to be implemented in C code later on. The recorded signal plots act as the reference for the next verification steps.
  • Model-in-the-loop simulation can also be used for detecting overflows of integer variables, and its results are used for simulation-based autoscaling.

Software-in-the-Loop Simulation

  • The code is generated and replaces the controller blocks in the simulation model (for example, the same plant and stimulus signals). TargetLink does this automatically in the background.
  • You still see the controller blocks, though it is the code that is executed on the host PC instead. The signal plots should be largely identical when compared to the results of model-in-the-loop simulation. If they are not, they can be analyzed to get a better understanding of the cause of the deviation and to fine-tune the fixed-point settings.

Processor-in-the-Loop Simulation

  • The generated code runs on an embedded processor, but because code that runs correctly on the host PC can still cause trouble, it has to be inspected further.
  • An off-the-shelf evaluation board is connected to the host PC, and the generated code is compiled with the target compiler and downloaded to the evaluation board.
  • TargetLink manages the communication between the host PC and the evaluation board. All these activities are automated and need no user interaction. Simulation on an evaluation board just takes two mouse clicks.

Features and Benefits of the Simulation Concept

Feature Description Benefit
  • MIL/SIL/PIL simulation at the click of a button
  • Switching from MIL to SIL or PIL simulation requires just one click
  • Powerful simulation environment
  • No need for separate test models, generation of S-functions or manual insertions into test harness models
  • Integrated data logging
  • Built-in data logging and result plotting for all simulation modes
  • No model modifications necessary
  • Available for all simulation modes
  • Direct comparison of MIL/SIL/PIL results
  • Automatical plotting of all simulation results in the same plot window
  • Display results of simulations in different modes directly and analyze deviations
  • Direct feedback whether code matches model simulation
  • Detailed signal analysis and deviation plots
  • Zoom signals to visually inspect deviations, display constraints (e.g., defined ranges), use cursor to scroll through signal histories, display signal values numerically or plot signal deviation
  • Get a clear picture of the signal behavior
  • Especially useful for conversion from floating-point to fixed-point

Further Verification Features in TargetLink

Feature Description
  • Integrated data logging and plotting
  • Built-in TargetLink blocks come with an integrated data logging functionality. In the block dialogs, you can specify whether to log the block output signals.
  • Run-time analysis for profiling the code
  • Processor-in-the-loop (PIL) simulation can also be used to profile the generated code. During PIL simulation, TargetLink automatically measures execution time and stack consumption directly on the target processor.
  • Code coverage analysis
  • You can assess how comprehensive tests are by using code coverage analysis. TargetLink offers C0 and C1 coverage analysis, also called statement coverage and decision coverage.
  • Model-code traceability
  • For improved traceability and simplified code reviews, code files can optionally be generated in HTML format, with hyperlinks for navigation from model to code and vice versa.

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