DS5203 FPGA Board1)

FPGA programmable per application

The DS5203 FPGA Board is designed for applications that require very fast, high-resolution signal preprocessing.

The end of life for this product has been set. Please see the footnote for more detailed information.

  • Completely user-programmable via the RTI FPGA Programming Blockset
  • Uses the Xilinx® System Generator (XSG) Simulink® Blockset
  • Basic set of I/O drivers on board, I/O extensible by piggyback modules

The DS5203 FPGA Board can be adapted to various tasks, so you can react flexibly to tougher requirements, such as signal conditioning, using new interfaces, or speeding up model parts. FPGAs are especially useful for relieving the processor board of tasks such as signal preprocessing during ECU development. Running at 100 MHz, the DS5203 board is ideal for application fields like engine knocking, cylinder pressure analysis, and electric drive projects. The DS5203 works closely together with the XSG model library.

Key Benefits

A field-programmable gate array (FPGA) is a semiconductor device consisting of logic elements that you can configure. The DS5203 FPGA Board features the freely programmable Xilinx Virtex®-5 FPGA with ISE support or the powerful Xilinx Kintex®-7 with Vivado® support. In addition, the board offers 6 ADC, 6 DAC and 16 digital I/O channels, and connection to the processor board via PHS bus. The number of I/O channels can be increased by piggyback modules.

Parameter Specification
DS5203 LX50 DS5203 SX95 DS5203 7K325 DS5203 7K410
General
  • User-programmable FPGA
  • User-programmable FPGA
  • User-programmable FPGA
  • User-programmable FPGA
FPGA
  • Xilinx® Virtex®-5 LX50T-1C
  • Logic cells: 46080 (Virtex®-5 slices: 7200; DSP slices: 48)
  • Distributed RAM: 480 kbit
  • Block RAM: 2160 kbit
  • Xilinx® Virtex®-5 SX95T-2C
  • Logic cells: 94298 (Virtex®-5 slices: 14720; DSP slices: 640)
  • Distributed RAM: 1520 kbit
  • Block RAM: 8784 kbit
  • Xilinx® Kintex®-7 K325
  • Logic cells: 326080 (Kintex®-7 slices: 50950; DSP slices: 840)
  • Distributed RAM: 4000 kbit
  • Block RAM: 16020 kbit
  • Xilinx® Kintex®-7 K410
  • Logic cells: 406720 (Kintex®-7 slices: 63550; DSP slices: 1540)
  • Distributed RAM: 5663 kbit
  • Block RAM: 28620 kbit
Xilinx® software support
  • Only ISE®
  • Only ISE®
  • Vivado®
  • Vivado®
Device timing
  • 100 MHz
  • 100 MHz
  • 100 MHz
  • 100 MHz
Digital I/O
  • 16 channels, usable as input or output
  • 16 channels, usable as input or output
  • 16 channels, usable as input or output
  • 16 channels, usable as input or output
    Input
  • Maximum input voltage: 15 V
  • Digital input: Threshold adjustable for each channel from 1 V to 7.5 V

Output

  • Digital output: Push-pull drivers; one output voltage can be selected for all channels: 3.3 V or 5 V
 Input
  • Maximum input voltage: 15 V
  • Digital input: Threshold adjustable for each channel from 1 V to 7.5 V

Output

  • Digital output: Push-pull drivers; one output voltage can be selected for all channels: 3.3 V or 5 V
 Input
  • Maximum input voltage: 15 V
  • Digital input: Threshold adjustable for each channel from 1 V to 7.5 V

Output

  • Digital output: Push-pull drivers; one output voltage can be selected for all channels: 3.3 V or 5 V
 Input
  • Maximum input voltage: 15 V
  • Digital input: Threshold adjustable for each channel from 1 V to 7.5 V

Output

  • Digital output: Push-pull drivers; one output voltage can be selected for all channels: 3.3 V or 5 V
Analog I/O   Input
  • 6 channels
  • Resolution: 14 bit pipelined
  • Sampling rate: 10 Msps
  • Input voltage range selectable for each channel: ±5 V or ±30 V
Output
  • 6 channels
  • Resolution: 14 bit
  • Update rate: 10 Msps
  • Output voltage range: ±10 V
 Input
  • 6 channels
  • Resolution: 14 bit pipelined
  • Sampling rate: 10 Msps
  • Input voltage range selectable for each channel: ±5 V or ±30 V
Output
  • 6 channels
  • Resolution: 14 bit
  • Update rate: 10 Msps
  • Output voltage range: ±10 V
 Input
  • 6 channels
  • Resolution: 14 bit pipelined
  • Sampling rate: 10 Msps
  • Input voltage range selectable for each channel: ±5 V or ±30 V
Output
  • 6 channels
  • Resolution: 14 bit
  • Update rate: 10 Msps
  • Output voltage range: ±10 V
 Input
  • 6 channels
  • Resolution: 14 bit pipelined
  • Sampling rate: 10 Msps
  • Input voltage range selectable for each channel: ±5 V or ±30 V
Output
  • 6 channels
  • Resolution: 14 bit
  • Update rate: 10 Msps
  • Output voltage range: ±10 V
Further interfaces

Slot for one I/O module for extending the analog and digital I/O (p. 453)
Connection for the angular processing unit (APU) bus
2 connectors for inter-FPGA communication
  Physical size 340 x 125 x 15 mm (13.4 x 4.9 x 0.6 in)
  Ambient temperature 0 ... 55 ºC (32 ... 131 ºF)
  Power supply +5 V ±5%, 2.5 A
+12 V ±5%, 0.7 A
-12 V ±5%, 0.1 A

The DS5203M1 Multi-I/O Module is a piggyback module for the DS5203 FPGA Board. It extends the available digital and analog I/O to give you more flexibility.

Technical Details

Parameter Specification
Digital I/O
  • 16 channels, usable as input or output
Analog I/O Input
  • Maximum input voltage: 15 V
  • Threshold for each channel adjustable from 1 V to 7.5 V
  Output
  • Push-pull drivers
  • One output voltage can be selected for all channels: 3.3 V or 5 V
Analog I/O Input
  • 6 channels
  • Resolution: 14 bit pipelined
  • Sampling rate: 10 MSPS
  • Input voltage range selectable for each channel: ±5 V or ±30 V
  Output
  • 6 channels
  • Resolution: 14 bit
  • Update rate: 10 MSPS
  • Output voltage range: ±10 V
Sensor supply
  • Adjustable
  • Output voltage range: 2 V to 20 V

The EV1099 Resolver SC Module is a transfer element for the DS5203 FPGA Board or the DS5203M1 Multi-I/O Module.
It offers special signal conditioning for electric drive applications, such as transformers for resolver simulation.
 
Additional features:
  • Configurable audio transformer for each of the 6 DAC channels
  • Switchable 220 Ω resistor for each of the 6 ADC channels

 

The module can be installed in a dSPACE Simulator Full-Size or Mid-Size. It is connected via ribbon cable to the DS5203 or DS5203M1, which are pin-compatible.

1)The end of life of the dSPACE PHS (peripheral high-speed) hardware for modular systems is planned for December 31, 2024. You can still buy the related products up to and including December 31, 2021. New Releases of dSPACE software will still support the dSPACE PHS hardware for modular systems until at least the end of 2023. After the end of life, no services of any kind will be available for these products. We advise against using the PHS hardware products in new projects. For new projects we recommend that you use SCALEXIO, the latest dSPACE technology for modular real-time systems.

Real-Time Interface (RTI) Automatic implementation of MATLAB®/Simulink®/Stateflow® models on dSPACE hardware RTI FPGA Programming Blockset Integrates FPGA models in dSPACE systems XSG Utils Library Ready-to-use function blocks for speeding up the implementation of FGPA models AC Motor Control Solution Control of diverse AC motors XSG Electric Component Library Plant models for FPGA-based simulations.
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