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Fraunhofer Institute Targets dSPACE Real-time Platform for Simulation of Virtual Circuits

May 7, 2013: Model-based design and simulation methods are the state-of-the-art to handle and verify the complex system behavior in the development process of integrated electronic components. This enables an early verification and testing of the overall system behavior using a virtual prototype. More and more integrated component (IC) developers use the C++ based modeling language SystemC/SystemC-AMS to design their entire system architecture as well as to develop the embedded software at a very early point in time.

Many suppliers of ICs are already offering SystemC/SystemC-AMS based models. Their customers use them within their own development process to ensure that components can be integrated in their system and to prevent specification errors and misinterpretations. The excellent capability of the language, to model different levels of abstraction allows the development of very fast simulating models with a sufficient accuracy by an appropriate level of detail. These models can be optimized to achieve real-time execution. The Fraunhofer Institute IIS/EAS in Dresden has implemented a solution to execute SystemC/SystemC-AMS on the dSPACE real-time platform.
The Fraunhofer Institute IIS/EAS provides libraries and code generators, included in their COSIDE® development environment, to support the dSPACE real-time hardware (DS1005/1006). This enables real-time Hardware in the Loop simulations for executable specifications and architectural level models based on SystemC/SystemC-AMS including digital and analog hardware as well as software. Developers are now able to test the specification of their mixed-signal systems in combination with already existing hardware components and the system environment long before the new component exists physically.
This technology additionally permits the reuse of high-level regression test environments developed during the concept and implementation phases in the laboratory to validate the first silicon sample. Such test environments are highly sophisticated and cover a wide range of functional and parameter tests. This will significantly increase the test coverage, reduce the validation effort and thus increase the product quality.  Furthermore this technology supports safety and security requirements.
This innovative technology will be demonstrated at the "Design Automation Conference (DAC)" from June 1 to June 6, 2013 in Austin/Texas (booth 2340).