May 09, 2012: During hardware-in-the-loop simulation, the dSPACE DS5203 FPGA Board performs signal preprocessing to reduce the computational load of the processor board. As of dSPACE Release 2012-A, the DS5203 provides a connection for an APU bus in addition to the user-programmable FPGA. The angular processing unit (APU) calculates the engine angle with high precision as a basis for providing I/O values to the HIL simulation.
The DS5203 can be used as a master or a slave. When it is the APU master, the angle values for the simulation model are computed and used on the FPGA itself, and if necessary transmitted to other I/O boards via the APU bus. As the APU slave, it receives the engine angle values from another dSPACE I/O board such as the DS2211 HIL I/O Board. The angle data can then also be used in the simulation models running on the DS5203.