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FPGA Basic

(based on Xilinx® System Generator)

dSPACE provides various real-time components with FPGAs that can be freely programmed by using either hand code (HDL) or a block-oriented environment. This training course focuses on the block-oriented approach. Xilinx® System Generator (XSG) is integrated directly in MATLAB®/Simulink® so that the procedure for modeling FPGA implementations is similar to the process for modeling familiar microprocessors.

This training course will equip you with the basic skills you need for successfully embedding applications on dSPACE FPGA hardware:

  • Set up a FPGA model
  • Exchange parameters between the processor and FPGA
  • Check the timing behavior and the FPGA’s resource consumption
  • Perform an FPGA build process
  • Embed the FPGA build result
  • Download/program the FPGA on the real-time system

You will also receive a brief overview and functional description of the Xilinx (XSG) third-party elements, which contain basic elements only.

The dSPACE XSG Utils Library provides more complex functions that enable you to model your design comfortably and quickly. Tasks such as integrating a 3-D look-up table or a 3-phase PWM generator on the FPGA can be completed with just a few clicks. The library also provides scope functionality, thereby enabling you to monitor the FPGA signals at the FPGA clock rate (e.g., 10 ns) in dSPACE ControlDesk® during online simulation. All library components are implemented as open XSG-based models and all main components can be tuned online. You will learn the skills for using the library and the dSPACE modeling structure.

The course provides all the basics required for embedding a real-time FPGA application, parameterizing the plant models, monitoring the current status, and also accessing the onboard I/O.

  • Engineers working on a freely programmable dSPACE FPGA
  • Necessary: Experience with MATLAB/Simulink

  • Building and embedding FPGA applications
  • Interfacing and configuring FPGA applications
  • Accessing the onboard I/O
  • Using the XSG Utils models to enhance the FPGA design

  • XSG Utils models
  • MATLAB/Simulink
  • Xilinx® System Generator (XSG)

  • Implementation of applications on a dSPACE FPGA Board
  • dSPACE XSG Utils Library
  • Parameterization of FPGA components during run time

DatesLocation and time Fee per person
November 21 - 22, 2017 Paderborn (Deutschland), 9:00 bis 17:15 Uhr € 1070 (plus tax)

20% discount for universities

When booked in combination with 'FPGA Electric Drives', the overall fee per person is € 1380 (plus tax)
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