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DS5001 Digital Waveform Capture Board

Capturing digital signals

The DS5001 Digital Waveform Capture Board has been designed to carry out the acquisition of complex, high-speed digital signals, such as pulse-width-modulated waveforms or position signals from various sensors. It is capable of evaluating various signal parameters, including frequency, phase shifts, and duty cycle.    

Application Areas

The application area of the DS5001 Digital Waveform Capture Board ranges from automotives through drives to robotics. The DS5001 is in active use in many hardware in the loop and rapid control prototyping applications. It can be connected to the engine position bus of the DS2211 HIL I/O Board. This lets you perform angle-synchronous signal capturing, with the DS5001 as either a time-base slave or the master. The board can also be connected to the time-base connector of the DS4002 Timing and Digital I/O Board or other DS5001 boards, and itself function as a time-base master for other boards.


Key Benefits

Capturing digital signals is a part of most control and hardware‑in‑the‑loop applications. However, with ordinary timing I/O, the speed, resolution, or number of channels often is not sufficient. And typically, complicated analysis algorithms are required. These usually have to be programmed in assembler language, which most users would prefer to avoid. You can overcome these limitations with the DS5001. The board records digital signals at a high speed for extremely flexible evaluation of frequency, phase, duty cycles, and other signal parameters.

Further Functions

The DS5001 Digital Waveform Capture Board includes 16 input channels that let you capture digital signals with a resolution of 25 ns. The board sees each signal as a series of rising and falling edges. The time stamp and polarity of each edge are stored. A processor board can use this data to perform any analysis you need. Event counters and sophisticated interrupt mechanisms enable you to evaluate not only frequencies and phases, but also signal characteristics such as jitter and missing pulses.

Parameter Specification
  • 16 timing I/O channels (inputs)
  • Event storage with dual-port memory (DPMEM) and first-in-first-out memory (FIFO)
  • Interrupt controller
  • Time-base connector
Interrupt controller
  • Interrupt on predefined number of events
  • Interrupt on event buffer full
  • Interrupt on input FIFO full
Timing I/O channels Time resolution
  • 25 ns
Sampling rate
  • Max. 40 MHz
Input frequency
  • Max. 20 MHz
Pulse-width range
  • 25 ns … 53.68 s
Edge detection
  • Separate edge detector for each channel
Detection type
  • Programmable rising and/or falling edge detection
Input voltage range (trigger level)
  • ±10 V (programmable)
Input voltage protection
  • ±35 V (continuous)
  • 80 mV … 2.8 V (selectable)
Edge detection
  • Rising and/or falling edge detection (programmable)
  • Trigger level -10 … +10 V (programmable in 256 steps)
Event storage
  • Dual-port RAM stores up to 512 events per channel
  • Events include 31-bit time stamp and edge polarity
  • Access to event storage from processor board
Event counters
  • 3 up counters (32-bit)
  • Each counter can be assigned to any channel
  • 3 up counters (32-bit)
  • Each counter can be assigned to any channel
  • Counter read and reset from processor board
Physical connections
  • 37-pin male Sub-D input connector
Host interface
  • One 8- or 16-bit ISA slot (power supply only)
Physical characteristics Physical size
  • 340 x 114 x 20 mm (13.4 x 4.9 x 0.8 in)
Ambient temperature
  • 0 … 70 ºC (32 … 158 ºF)
Power supply
  • +5 V ±5%, 2.5 A



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