FPGA Basic

(based on Xilinx^® Vitis^™ Model Composer HDL Library, the former Xilinx^® System Generator (XSG) Blockset)

dSPACE provides various real-time components with FPGAs that can be freely programmed by using either hand code (HDL) or a block-oriented environment. This training course focuses on the block-oriented approach. Xilinx^® Vitis<™ Model Composer HDL Library, the former Xilinx^® System Generator Blockset, is integrated directly in MATLAB^®/Simulink^® so that the procedure for modeling FPGA implementations is similar to the process for modeling commonly used microprocessors. The training uses a SCALEXIO real-time system.

This training course will equip you with the basic skills you need for successfully embedding applications on dSPACE FPGA hardware: set up a FPGA model, exchange parameters between the processor and FPGA, check the timing behavior and the FPGA’s resource consumption, perform an FPGA build process, embed the FPGA build result, and download/program the FPGA on the real-time system.

You will also receive a brief overview and functional description of the Xilinx (XSG) third-party elements, which contain basic elements only.

The dSPACE XSG Utils Library provides more complex functions that enable you to model your design comfortably and quickly. Tasks such as integrating a 3-D look-up table or a 3-phase PWM generator on the FPGA can be completed with just a few clicks. Moreover, the library provides scope functionality, thereby enabling you to monitor the FPGA signals at the FPGA clock rate (e.g., 8 ns) in ControlDesk during online simulation. All library components are implemented as open XSG-based models and all main components can be tuned online. You will learn the skills for using the library and the dSPACE modeling structure.

The course provides the basics required for embedding a real-time FPGA application, parameterizing the plant models, monitoring the current status, and accessing the onboard I/O.